Instruction Set Architecture (ISA)

The pccx v002 ISA is a fixed-length, VLIW-style 64-bit format with five opcodes: GEMV, GEMM, MEMCPY, MEMSET, and CVO. The design follows three principles:

• Hardware independence: the encoding is decoupled from any specific device’s resource budget.

• CISC-style macros: one instruction kicks off thousands of MAC cycles.

• Dispatch-centric: instructions are decoded into control μops and memory μops as soon as they land, and those are handed off to the back end.

• Instruction Encoding
• Per-Instruction Encoding
• Per-Instruction Dataflow

Download the offline guidebook (PDF)

A signoff-ready typeset version of this ISA reference — same tables, same numbers, offline-readable — is downloadable as a PDF:

pccx v002 ISA Guidebook (PDF)

The PDF is regenerated from main.tex at the repository root; the LaTeX source is the single authoring entry point for the offline book, while this HTML portal remains the living reference for the web.

Note

The authoritative ISA type definitions live in the v002 RTL repo at hw/rtl/NPU_Controller/NPU_Control_Unit/ISA_PACKAGE/isa_pkg.sv (external: pccxai/pccx-FPGA-NPU-LLM-kv260). Encoding tables on the pages below must stay in sync with that package — see ISA Type Package.